//////////////////////////////////////////////////////////////////////////////////
//				Data Memory					//
//						    reference : lecure ppt	//
//////////////////////////////////////////////////////////////////////////////////


module DMEM(iClk,iWe,iAddr,iWdata,oRdata    , M0, M1, M5, M16, M17); //Ms for test

input iClk; 		// clock
input iWe;		// write enable
input [7:0] iAddr;	// adrress
input [7:0] iWdata;	// write data
output [7:0] oRdata;	// read data

output [7:0] M0, M1, M5, M16, M17; //for test


reg [7:0] RAM[255:0];

assign M0=RAM[0]; //for test
assign M1=RAM[1];
assign M5=RAM[5];
assign M16=RAM[16];
assign M17=RAM[17]; //test ends here

assign oRdata = RAM[iAddr];

always @ (posedge iClk)
begin
	if (iWe)
		RAM[iAddr] <= iWdata;
end

endmodule